View MC100E211FN_741991.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MC10E211, MC100E211 5V ECL 1:6 Differential Clock Distribution Chip
Description
The MC10E/100E211 is a low skew 1:6 fanout device designed explicitly for low skew clock distribution applications. The E211 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open in which case it will be pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative transition of the CLK (or SCLK) input. The enabling function is synchronous so that the outputs will only be enabled/disabled when the outputs are already in the LOW state. In this way the problem of runt pulse generation during the disable operation is avoided. Note that the internal flip flop is clocked on the falling edge of the input clock edge, therefore all associated specifications are referenced to the negative edge of the CLK input. The output transitions of the E211 are faster than the standard ECLinPS edge rates. This feature provides a means of distributing higher frequency signals than capable with the E111 device. Because of these edge rates and the tight skew limits guaranteed in the specification, there are certain termination guidelines which must be followed. For more details on the recommended termination schemes please refer to the applications information section of this data sheet. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
Features
http://onsemi.com
PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
MCxxxE211FNG AWLYYWW
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.
* * * * * * * * *
Guaranteed Low Skew Specification Synchronous Enabling/Disabling Multiplexed Clock Inputs VBB Output for Single-Ended Use Common and Individual Enable/Disable Control High Bandwidth Output Transistors PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V Internal Input 75 kW Pulldown Resistors
* ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
* Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
* Moisture Sensitivity Level: Pb = 1; Pb-Free = 3 * * *
For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 457 devices Pb-Free Packages are Available*
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 12
1
Publication Order Number: MC10E211/D
MC10E211, MC100E211
EN4 EN5 VCC0 EN3 SEL SCLK VEE CLK CLK VBB 26 27 28 1 2 3 4 5 6 7 8 9 10 11 Q0 25 24 23 Q5 22 Q5 21 Q4 20 Q4 19 18 17 16 15 14 13 12 Q3 Q3 VCC Q2 Q2 Q1 Q1
Table 1. PIN DESCRIPTION
PIN EN0-EN5 SEL SCLK CLK, CLK CEN Q0-Q5, Q0-Q5 VBB VCC, VCCO VEE NC FUNCTION ECL Enable ECL Select (Clock) ECL Single Clock ECL Differential Clock ECL Common Enable ECL Differential Outputs Reference Voltage Output Positive Supply Negative Supply No Connect
CEN EN2
EN1 EN0 VCC0 Q0
*All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC-28 (Top View)
Q0 Q0 EN0 DQ
Table 2. FUNCTION TABLE
CLK H/L X Z* SCLK X H/L Z* SEL L H X ENx L L H Q CLK SCLK L
*Z = Negative transition of CLK or SCLK CLK CLK SCLK SEL EN1-4 CEN Q5 Q5 EN5 DQ 0 1 DQ BITS 1-4 Q1-4 Q1-4
VBB
Figure 2. Logic Diagram
http://onsemi.com
2
MC10E211, MC100E211
Table 3. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC VEE Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) PECL Operating Range NECL Operating Range Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board PLCC-28 PLCC-28 PLCC-28 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 -8 6 -6 50 100 0.5 0 to +85 -65 to +150 63.5 43.5 22 to 26 4.2 to 5.7 -5.7 to -4.2 265 265 Unit V V V V mA mA mA C C C/W C/W C/W V V C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
http://onsemi.com
3
MC10E211, MC100E211
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 3) Input HIGH Current Input LOW Current 0.5 0.3 3980 3050 3830 3050 3.62 2.4 Min Typ 119 4070 3210 3995 3285 Max 160 4160 3370 4160 3520 3.74 4.6 4020 3050 3870 3050 3.65 2.4 Min 25C Typ 119 4105 3210 4030 3285 Max 160 4190 3370 4190 3520 3.75 4.6 4090 3050 3940 3050 3.69 2.4 Min 85C Typ 119 4185 3227 4110 3302 Max 160 4280 3405 4280 3555 3.81 4.6 Unit mA mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.3 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VE E = -5.0 V (Note 4)
0C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) Input HIGH Current Input LOW Current 0.5 0.3 -1020 -1950 -1170 -1950 -1.38 -2.6 Min Typ 119 -930 -1790 -1005 -1715 Max 160 -840 -1630 -840 -1480 -1.27 -0.4 -980 -1950 -1130 -1950 -1.35 -2.6 Min 25C Typ 119 -895 -1790 -970 -1715 Max 160 -810 -1630 -810 -1480 -1.25 -0.4 -910 -1950 -1060 -1950 -1.31 -2.6 Min 85C Typ 119 -815 -1773 -890 -1698 Max 160 -720 -1595 -720 -1445 -1.19 -0.4 Unit mA mV mV mV mV V V
IIH IIL
150 0.5 0.065
150 0.3 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.06 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
http://onsemi.com
4
MC10E211, MC100E211
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 7)
0C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current Input LOW Current 0.5 0.3 3975 3190 3835 3190 3.62 2.4 Min Typ 119 4050 3295 3975 3355 Max 160 4120 3380 4120 3525 3.74 4.6 3975 3190 3835 3190 3.62 2.4 Min 25C Typ 119 4050 3255 3975 3355 Max 160 4120 3380 4120 3525 3.74 4.6 3975 3190 3835 3190 3.62 2.4 Min 85C Typ 137 4050 3260 3975 3355 Max 164 4120 3380 4120 3525 3.74 4.6 Unit mA mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.5 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 8. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = -5.0 V (Note 10)
0C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 11) Output LOW Voltage (Note 11) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 12) Input HIGH Current Input LOW Current 0.5 0.3 -1025 -1810 -1165 -1810 -1.38 -2.6 Min Typ 119 -950 -1705 -1025 -1645 Max 160 -880 -1620 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -2.6 Min 25C Typ 119 -950 -1745 -1025 -1645 Max 160 -880 -1620 -880 -1475 -1.26 -0.4 -1025 -1810 -1165 -1810 -1.38 -2.6 Min 85C Typ 137 -950 -1740 -1025 -1645 Max 164 -880 -1620 -880 -1475 -1.26 -0.4 Unit mA mV mV mV mV V V
IIH IIL
150 0.5 0.25
150 0.5 0.2
150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary -0.46 V / +0.8 V. 11. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 12. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
http://onsemi.com
5
MC10E211, MC100E211
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = -5.0 V (Note 13)
0C Symbol fMAX tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output CLK to Q (Diff) CLK to Q (SE) SCLK to Q SEL to Q Disable Time CLK or SCLK to Q (Note 15) Part-to-Part Skew CLK (Diff) to Q CLK (SE), SCLK to Q Within-Device Skew (Note 14) Random Clock Jitter (RMS) Setup Time ENx to CLK CEN to CLK (Note 15) Hold Time CLK to ENx, CEN (Note 15) Minimum Input Swing (CLK) (Note 16) Rise/Fall Times (20 - 80%) 200 200 900 0.25 150 50 <1 -100 0 600 1.0 400 200 200 900 0.25 150 795 745 650 745 Min Typ 700 930 930 900 970 600 1065 1115 1085 1195 800 270 370 75 805 755 650 755 Max Min 25C Typ 700 940 940 910 980 600 1075 1125 1095 1205 800 270 370 75 <1 200 200 900 1.0 400 0.25 150 -100 0 600 1.0 400 825 775 650 775 Max Min 85C Typ 700 960 960 930 1000 600 1095 1145 1115 1225 800 270 370 75 Max Unit MHz ps
tPHL tskew
ps ps
50 <1 -100 0 160
tJITTER ts
ps ps
th VPP tr tf
ps V ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. 10 Series: VEE can vary -0.46 V / +0.06 V. 100 Series: VEE can vary -0.46 V / +0.8 V. 14. Within-Device skew is defined for identical transitions on similar paths through a device. 15. Setup, Hold and Disable times are all relative to a falling edge on CLK or SCLK. 16. Minimum input swing for which AC parameters are guaranteed. Full DC ECL output swings will be generated with only 50 mV input swings.
http://onsemi.com
6
MC10E211, MC100E211
APPLICATIONS INFORMATION
General Description
The MC10E/100E211 is a 1:6 fanout tree designed explicitly for low skew high speed clock distribution. The device was targeted to work in conjunction with the E111 device to provide another level of flexibility in the design and implementation of clock distribution trees. The individual synchronous enable controls and multiplexed clock inputs make the device ideal as the first level distribution unit in a distribution tree. The device provides the ability to distribute a lower speed scan or test clock along with the high speed system clock to ease the design of system diagnostics and self test procedures. The individual enables could be used to allow for the disabling of individual cards on a backplane in fault tolerant designs. Because of lower fanout and larger skews the E211 will not likely be used as an alternative to the E111 for the bulk of the clock fanout generation. Figure 3 shows a typical application combining the two devices to take advantage of the strengths of each.
E111
situations between cards there will be no AC performance or noise margin loss for the differential CLK inputs. For situations where TTL clocks are required the E211 can be interfaced with the H641 or H643 ECL to TTL Clock Distribution Chips. The H641 is a single supply 1:9 PECL to TTL device while the H643 is a 1:8 dual supply standard ECL to TTL device. By combining the superior skew performance of the E211, or E111, with the low skew translating capabilities of the H641 and H643 very low skew TTL clock distribution networks can be realized.
Handling Open Inputs and Outputs
Q0
E211
Q0 BACKPLANE
Q8
E111
Q5
Q0
Q8
Figure 3. Standard E211 Application Using the E211 in PECL Designs
The E211 device can be utilized very effectively in designs utilizing only a +5 V power supply. Since the internal switching reference levels are biased off of the VCC supply the input thresholds for the single-ended inputs will vary with VCC. As a result the single-ended inputs should be driven by a device on the same board as the E211. Driving these inputs across a backplane where significant differences between the VCC's of the transmitter and receiver can occur can lead to AC performance and/or significant noise margin degradations. Because the differential I/O does not use a switching reference, and due to the CMR range of the E211, even under worst case VCC
All of the input pins of the E211 have a 50 kW to 75 kW pulldown resistor to pull the input to VEE when left open. This feature can cause a problem if the differential clock inputs are left open as the input gate current source transistor will become saturated. Under these conditions the outputs of the CLK input buffer will go to an undefined state. It is recommended, if possible,that the SCLK input should be selected any time the differential CLK inputs are allowed to float. The SCLK buffer, under open input conditions, will maintain a defined output state and thus the Q outputs of the device will be in a defined state (Q = LOW). Note that if all of the inputs are left open the differential CLK input will be selected and the state of the Q outputs will be undefined. With the simultaneous switching characteristics and the tight skew specifications of the E211 the handling of the unused outputs becomes critical. To minimize the noise generated on the die all outputs should be terminated in pairs, i.e. both the true and complement outputs should be terminated even if only one of the outputs will be used in the system. With both complementary pairs terminated the current in the VCC pins will remain essentially constant and thus inductance induced voltage glitches on VCC will not occur. VCC glitches will result in distorted output waveforms and degradations in the skew performance of the device. The package parasitics of the PLCC-28 cause the signals on a given pin to be influenced by signals on adjacent pins. The E211 is characterized and tested with all of the outputs switching, therefore the numbers in the data book are guaranteed only for this situation. If all of the outputs of the E211 are not needed and there is a desire to save power the unused output pairs can be left unterminated. Unterminated outputs can influence the propagation delay on adjacent pins by 15 ps - 20 ps. Therefore under these conditions this 15 ps - 20 ps needs to be added to the overall skew of the device. Pins which are separated by a package corner are not considered adjacent pins in the context of propagation delay influence. Therefore as long as all of the outputs on a single side of the package are terminated the specification limits in the data sheet will apply.
http://onsemi.com
7
MC10E211, MC100E211
APPLICATIONS INFORMATION
Differential versus Single-Ended Use
As can be seen from the data sheet, to minimize the skew of the E211 the device must be used in the differential mode. In the single-ended mode the propagation delays are dependent on the relative position of the VBB switching reference. Any VBB offset from the center of the input swing will add delay to either the TPLH or TPHL and subtract delay from the other. This increase and decrease in delay will lead to an increase in the duty cycle skew and thus part-to-part skew. The within-device skew will be independent of the VBB and therefore will be the same regardless of whether the device is driven differentially or single-ended. For applications where part-to-part skew or duty cycle skew are not important the advantages of single-ended clock distribution may lead to its use. Using single-ended interconnect will reduce the number of signal traces to be routed, but remember that all of the complementary outputs still need to be terminated therefore there will be no reduction in the termination components required. To use the E211 with a single-ended input the arrangement pictured in Figure 5 should be used. If the input to the differential CLK inputs are AC coupled as pictured in Figure 4 the dependence on a centered VBB reference is removed. The situation pictured will ensure that the input is centered around the bias set by the VBB. As a result when AC coupled the AC specification limits for a differential input can be used. For more information on AC coupling please refer to the interfacing section of the design guide in the ECLinPS data book.
Using the Enable Pins
IN 0.001mF IN 50 W
0.01mF
VBB
Figure 4. AC Coupled Input
IN
IN
0.01 mF
Both the common enable (CEN) and the individual enables (ENx) are synchronous to the CLK or SCLK input depending on which is selected. The active low signals are clocked into the enable flip flops on the negative edges of the E211 clock inputs. In this way the devices will only be disabled when the outputs are already in the LOW state. The internal propagation delays are such that the delay to the output through the distribution buffers is less than that through the enable flip flops. This will ensure that the disabling of the device will not slice any time off the clock pulse. On initial power up the enable flip flops will randomly attain a stable state, therefore precautions should be taken on initial power up to ensure the E211 is in the desired state.
VBB
Figure 5. Single-Ended Input
http://onsemi.com
8
MC10E211, MC100E211
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC10E211FN MC10E211FNG MC10E211FNR2 MC10E211FNR2G MC100E211FN MC100E211FNG MC100E211FNR2 MC100E211FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
http://onsemi.com
9
MC10E211, MC100E211
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
http://onsemi.com
10
MC10E211, MC100E211
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
http://onsemi.com
11
MC10E211/D

▲Up To Search▲

Price & Availability of MC100E211FN

	To Download MC100E211FN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .